A slew-rate controlled output driver using PLL as compensation circuit.

A slew-rate controlled output driver using PLL as compensation circuit.

A slew-rate controlled output driver adopting the delay compensation method has been implemented using 0.18-μm CMOS process for storage device interface. A phase-locked loop (PLL) is used to generate compensation current and constant delay time. The compensation current reduces the slew-rate variati...

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Manylion Llyfryddiaeth
Cyhoeddwyd yn:IEEE Journal of solid state circuits 38, 7 (2003).
Prif Awdur: Soon-Kyun Shin
Fformat: Erthygl
Iaith:English
Pynciau:
0.18 micron.
15 to 40 pF.
CMOS process.
PLL compensation circuit.
PVT variation.
UDMA100 interface.
Current compensation.
Delay compensation.
Output driver.
Phase locked loop.
Slew rate control.
Storage device interface.
Voltage controlled oscillator.