A 4-Gb/s CMOS clock and data recovery circuit using 1

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-μm standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumptio...

詳細記述