A 4-Gb/s CMOS clock and data recovery circuit using 1

A 4-Gb/s CMOS clock and data recovery circuit using 1

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-μm standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumptio...

Full description

Bibliographic Details
Published in:IEEE Journal of solid state circuits 38, 7 (2003).
Main Author: Seong-Jun Song
Format: Article
Language:English
Subjects:
0.25 micron.
1/8-rate clock technique.
2.5 V.
4 Gbit/s.
6 bit.
70 mW.
CDR.
CMOS.
Active inductor loads.
Bit error rate.
Clock and data recovery circuit.
Common-mode rejection ratio differential amplifier.
Duty-cycle correction.
Folded differential fine control.
Half-quadrature clocks.
Jitter.
Linear phase detector.
Low pass filter.
Output buffers.
Phase noise.
Power consumption.
Pseudorandom bit sequence input data.
Ring oscillator configuration.
Voltage-controlled oscillator.