Design and performance testing of a 2.29-GB

Design and performance testing of a 2.29-GB

This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mW of power consumption in a 0.18-μm CMOS standard cell technology. This integrated circuit implements the Rijndael...

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Detalles Bibliográficos
Publicado en:IEEE Journal of solid state circuits 38, 3 (2003).
Autor Principal: Verbauwhede, I.
Formato: Artigo
Idioma:English
Subjects:
0.18 micron.
2.29 GB/s.
25 to 256 bit.
56 mW.
AES compliant encryption chip.
Advanced Encryption Standard.
CMOS standard cell technology.
Rijndael processor.
Block lengths.
Chip architecture.
Design optimizations.
Encryption throughput.
Key lengths.
Power consumption.
Secret key cryptography.