Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era.

Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era.

Several physical phenomena in highly scaled CMOS technology have now become first-order elements affecting the electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others can have significant inf...

詳細記述

書誌詳細
出版年:IEEE Journal of solid state circuits 38, 3 (2003).
第一著者: Diaz, C.H
フォーマット: 論文
言語:English
主題:
STI mechanical stress.
SoC era.
Application-dependent scaling tradeoffs.
Circuit design interlock.
Circuit optimization.
Circuit-level device modeling.
Direct tunneling.
Electrical behavior.
First-order elements.
Gate dielectrics.
Gate line-edge roughness.
Gate-dielectric thickness.
Highly scaled CMOS technology.
Process design interlock.
Shallow trench isolation depth.
Transistor current density dependency.