APA (7th ed.) Citation

Diaz, C. Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era. IEEE Journal of solid state circuits.

Chicago Style (17th ed.) Citation

Diaz, C.H. "Process and Circuit Design Interlock for Application-dependent Scaling Tradeoffs and Optimization in the SoC Era." IEEE Journal of Solid State Circuits .

MLA (9th ed.) Citation

Diaz, C.H. "Process and Circuit Design Interlock for Application-dependent Scaling Tradeoffs and Optimization in the SoC Era." IEEE Journal of Solid State Circuits, .