Delwedd Flaen

Timing analysis and simulation for signal integrity engineers

Manylion Llyfryddiaeth
Prif Awdur: Edlund, Greg
Fformat: Llyfr
Iaith:Saesneg
Cyhoeddwyd: Upper Saddle River, N.J. Prentice Hall c2008.
Pynciau:
Timing circuits > Design and construction.
Digital electronics > Design and construction.
Signal processing > Digital techniques.
Mynediad Ar-lein:Table of contents only