Implementation of a 32-bit dual core ARM7 microprocessor with single level cache
Shared-memory multiprocessors have become a cost-effective way of providing increased computing power and speed, mainly because they utilize low-cost microprocessors interconnected with shared memory modules. However, memory access tends to become a performance bottleneck due to multiple processors...
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| Drugi avtorji: | , , |
| Format: | Thesis |
| Jezik: | English |
| Izdano: |
2008.
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