Implementation of a 32-bit dual core ARM7 microprocessor with single level cache

Shared-memory multiprocessors have become a cost-effective way of providing increased computing power and speed, mainly because they utilize low-cost microprocessors interconnected with shared memory modules. However, memory access tends to become a performance bottleneck due to multiple processors...

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Detalles Bibliográficos
Autor Principal: Castro, Janelle Legaspi
Outros autores: Lomibao, Love Tulagan, Santos, Aaron Peter Paul Catuncan, Tolledo, Mark Neptaly Timajo
Formato: Thesis
Idioma:English
Publicado: 2008.
Subjects: