Implementation of a 32-bit dual core ARM7 microprocessor with single level cache
Shared-memory multiprocessors have become a cost-effective way of providing increased computing power and speed, mainly because they utilize low-cost microprocessors interconnected with shared memory modules. However, memory access tends to become a performance bottleneck due to multiple processors...
主要作者: | |
---|---|
其他作者: | , , |
格式: | Thesis |
語言: | English |
出版: |
2008.
|
主題: |