A study of floating-point architectures for pipelined RISC processors
As embedded applications become more complex, the demand for computing power increases. To achieve this needed increase in the computing performance of embedded microprocessors, improved implementations of floating-point units (FPUs)are used. However, no structured methodology is available in design...
| প্রধান লেখক: | |
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| বিন্যাস: | গবেষণাপত্র |
| ভাষা: | English |
| প্রকাশিত: |
2005.
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| বিষয়গুলি: |