A study of floating-point architectures for pipelined RISC processors
As embedded applications become more complex, the demand for computing power increases. To achieve this needed increase in the computing performance of embedded microprocessors, improved implementations of floating-point units (FPUs)are used. However, no structured methodology is available in design...
| المؤلف الرئيسي: | |
|---|---|
| التنسيق: | أطروحة |
| اللغة: | English |
| منشور في: |
2005.
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| الموضوعات: |