APA引文

Dioquino, D. A. M., Rosario, K. J. S., Supe, H. F., & Zarsuela, J. V. (2007). Design and implementation of a 32-Bit dual core capable DLX microprocessor with single-level cache.

Chicago Style (17th ed.) Citation

Dioquino, Darryl Aldrin M., Katrina Joy S. Rosario, Homer F. Supe, and Jestoni V. Zarsuela. Design and Implementation of a 32-Bit Dual Core Capable DLX Microprocessor with Single-level Cache. 2007.

MLA引文

Dioquino, Darryl Aldrin M., et al. Design and Implementation of a 32-Bit Dual Core Capable DLX Microprocessor with Single-level Cache. 2007.