Dioquino, D. A. M., Rosario, K. J. S., Supe, H. F., & Zarsuela, J. V. (2007). Design and implementation of a 32-Bit dual core capable DLX microprocessor with single-level cache.
Citace podle Chicago (17th ed.)Dioquino, Darryl Aldrin M., Katrina Joy S. Rosario, Homer F. Supe, a Jestoni V. Zarsuela. Design and Implementation of a 32-Bit Dual Core Capable DLX Microprocessor with Single-level Cache. 2007.
Citace podle MLA (9th ed.)Dioquino, Darryl Aldrin M., et al. Design and Implementation of a 32-Bit Dual Core Capable DLX Microprocessor with Single-level Cache. 2007.
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