Digital timing macromodeling for VLSI design verification

Digital timing macromodeling for VLSI design verification

Xehetasun bibliografikoak
Egile nagusia: Kong, Jeong-Taek 1959-
Beste egile batzuk: Overhauser, David 1961-
Formatua: Liburua
Hizkuntza:English
Argitaratua: Boston Kluwer Academic c1995.
Saila:The Kluwer international series in enginering and computer science SECS 319
Gaiak:
Integrated circuits > Very large scale integration > Design and construction > Data processing.
Integrated circuits > Verification > Data processing.
Computer-aided design.