Digital timing macromodeling for VLSI design verification

Digital timing macromodeling for VLSI design verification

Bibliografiset tiedot
Päätekijä: Kong, Jeong-Taek 1959-
Muut tekijät: Overhauser, David 1961-
Aineistotyyppi: Kirja
Kieli:English
Julkaistu: Boston Kluwer Academic c1995.
Sarja:The Kluwer international series in enginering and computer science SECS 319
Aiheet:
Integrated circuits > Very large scale integration > Design and construction > Data processing.
Integrated circuits > Verification > Data processing.
Computer-aided design.