A study of the effects of pipeline modification techniques on the performance and power consumption of the DLX microprocessor
In this thesis, two Stake-skip pipeline-level power optimization techniques namely: (1) the Stage-skip IF and (2) the Stage-skip MEM techniques are studied. These techniques bypass stages that are not needed in the execution of certain instructions, thus effectively reducing the power consumption of...
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| Format: | Thesis |
| Language: | English |
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2004.
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