A study of selective power-down techniques for low-power RISC microprocessor design
In this thesis, selective power-down techniques for low-power RISC microprocessor design sre studied. Selective-power down techniques are register transfer level power optimization techniques that target dynamic switching power. These techniques effectively reduce power consumption by selectively sh...
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| Formato: | Thesis |
| Idioma: | English |
| Publicado em: |
2004.
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