A study of selective power-down techniques for low-power RISC microprocessor design

A study of selective power-down techniques for low-power RISC microprocessor design

In this thesis, selective power-down techniques for low-power RISC microprocessor design sre studied. Selective-power down techniques are register transfer level power optimization techniques that target dynamic switching power. These techniques effectively reduce power consumption by selectively sh...

Täydet tiedot

Bibliografiset tiedot
Päätekijä: Khalid, Sihawi Abdulhamid
Aineistotyyppi: Opinnäyte
Kieli:English
Julkaistu: 2004.
Aiheet:
RISC microprocessors > Statistical power analysis.
RISC microprocessors > Switching power supplies.
Clock gating.
Control signal gating.
Precomputation.