A study of selective power-down techniques for low-power RISC microprocessor design

A study of selective power-down techniques for low-power RISC microprocessor design

In this thesis, selective power-down techniques for low-power RISC microprocessor design sre studied. Selective-power down techniques are register transfer level power optimization techniques that target dynamic switching power. These techniques effectively reduce power consumption by selectively sh...

Ausführliche Beschreibung

Bibliographische Detailangaben
1. Verfasser: Khalid, Sihawi Abdulhamid
Format: Abschlussarbeit
Sprache:English
Veröffentlicht: 2004.
Schlagworte:
RISC microprocessors > Statistical power analysis.
RISC microprocessors > Switching power supplies.
Clock gating.
Control signal gating.
Precomputation.