A study of selective power-down techniques for low-power RISC microprocessor design

In this thesis, selective power-down techniques for low-power RISC microprocessor design sre studied. Selective-power down techniques are register transfer level power optimization techniques that target dynamic switching power. These techniques effectively reduce power consumption by selectively sh...

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Manylion Llyfryddiaeth

Prif Awdur:	Khalid, Sihawi Abdulhamid
Fformat:	Traethawd Ymchwil
Iaith:	English
Cyhoeddwyd:	2004.
Pynciau:	RISC microprocessors > Statistical power analysis. RISC microprocessors > Switching power supplies. Clock gating. Control signal gating. Precomputation.