An asynchronous single-precision floating-point arithmetic unit
A transistor-level design of an asynchronous single-precision floating-point arithmetic unit is designed and tested using Cadence software. It uses CMOS (complementary metal oxide semiconductor) and DCVS (differential cascode voltage switch) logic in a 0.35 um process. Dual-rail signals are used for...
| Tác giả chính: | |
|---|---|
| Định dạng: | Luận văn |
| Ngôn ngữ: | English |
| Được phát hành: |
2003.
|
| Những chủ đề: |