A matrix representation for the verification of well-handledness of the Robustness Diagram with loop and time controls
Well-handledness in Robustness Diagrams with Loop and Time Controls (RDLT) is important, as it ensures proper termination and liveness for all workflows. Moreover, verifying well-handledness in Robustness Diagrams with Loop and Time Controls provides a structural method to verify classical soundness...
| Autor Principal: | |
|---|---|
| Outros autores: | |
| Formato: | Thesis |
| Idioma: | English |
| Subjects: |