ASIC design and synthesis RTL design using Verilog

ASIC design and synthesis RTL design using Verilog

Bibliografski detalji
Glavni autor: Taraate, Vaibbhav (Autor)
Format: Electronic Resource
Jezik:English
Izdano: Singapore Springer [2021]
Teme:
Application-specific integrated circuits > Design.
Verilog (Computer hardware description language)
Electronic books.
Online pristup:Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access