ASIC design and synthesis RTL design using Verilog

ASIC design and synthesis RTL design using Verilog

Sonraí bibleagrafaíochta
Príomhchruthaitheoir: Taraate, Vaibbhav (Údar)
Formáid: Electronic Resource
Teanga:English
Foilsithe / Cruthaithe: Singapore Springer [2021]
Ábhair:
Application-specific integrated circuits > Design.
Verilog (Computer hardware description language)
Electronic books.
Rochtain ar líne:Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access