ASIC design and synthesis RTL design using Verilog

ASIC design and synthesis RTL design using Verilog

Xehetasun bibliografikoak
Egile nagusia: Taraate, Vaibbhav (Egilea)
Formatua: Electronic Resource
Hizkuntza:English
Argitaratua: Singapore Springer [2021]
Gaiak:
Application-specific integrated circuits > Design.
Verilog (Computer hardware description language)
Electronic books.
Sarrera elektronikoa:Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access