ASIC design and synthesis RTL design using Verilog

ASIC design and synthesis RTL design using Verilog

ग्रंथसूची विवरण
मुख्य लेखक: Taraate, Vaibbhav (लेखक)
स्वरूप: Electronic Resource
भाषा:English
प्रकाशित: Singapore Springer [2021]
विषय:
Application-specific integrated circuits > Design.
Verilog (Computer hardware description language)
Electronic books.
ऑनलाइन पहुंच:Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access