ASIC design and synthesis RTL design using Verilog

ASIC design and synthesis RTL design using Verilog

Detalles Bibliográficos
Autor Principal: Taraate, Vaibbhav (Author)
Formato: Electronic Resource
Idioma:English
Publicado: Singapore Springer [2021]
Subjects:
Application-specific integrated circuits > Design.
Verilog (Computer hardware description language)
Electronic books.
Acceso en liña:Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access