ASIC design and synthesis RTL design using Verilog

ASIC design and synthesis RTL design using Verilog

Библиографические подробности
Главный автор: Taraate, Vaibbhav (Автор)
Формат: Electronic Resource
Язык:English
Опубликовано: Singapore Springer [2021]
Предметы:
Application-specific integrated circuits > Design.
Verilog (Computer hardware description language)
Electronic books.
Online-ссылка:Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access