ASIC design and synthesis RTL design using Verilog

ASIC design and synthesis RTL design using Verilog

Bibliografiset tiedot
Päätekijä: Taraate, Vaibbhav (Tekijä)
Aineistotyyppi: Electronic Resource
Kieli:English
Julkaistu: Singapore Springer [2021]
Aiheet:
Application-specific integrated circuits > Design.
Verilog (Computer hardware description language)
Electronic books.
Linkit:Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access