Cita APA (7a ed.)

Taraate, V. (2021). ASIC design and synthesis: RTL design using Verilog. Springer. https://doi.org/10.1007/978-981-33-4642-0

Cita Chicago Style (17a ed.)

Taraate, Vaibbhav. ASIC Design and Synthesis: RTL Design Using Verilog. Singapore: Springer, 2021. https://doi.org/10.1007/978-981-33-4642-0.

Cita MLA (9a ed.)

Taraate, Vaibbhav. ASIC Design and Synthesis: RTL Design Using Verilog. Springer, 2021. https://doi.org/10.1007/978-981-33-4642-0.