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IEEE Journal of solid state circuits
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IEEE Journal of solid state circuits
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A 160K Gates
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Lin, C.-C
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212
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.
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Noda, H.
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An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I
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Kim, K.-h
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214
An 8.1-ns Column-Access 1.6-Gb/s 4 Multiplexed Data-Transfer Scheme.
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Fujisawa, H.
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A 0.1-μm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation.
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Kang, S.
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216
A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB
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Takeuchi, K.
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A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.
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Khellah, M.
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