Showing 1,061 - 1,070 results of 1,209 for search '"memory."', query time: 0.02s Refine Results
  1. 1061

    The wishful memory of interpersonal responsiveness. [article]. by Lemay, Edward P.

    Analytics

    The wishful memory of interpersonal responsiveness. [article].
  2. 1062

    Trust and biased memory of transgressions in romantic relationships. [article]. by Luchies, Laura B.

    Analytics

    Trust and biased memory of transgressions in romantic relationships. [article].
  3. 1063

    Narrating the dictator(ship) social memory, Marcos and Ilokano literature after the 1986 revolution. by Galam, Roderick G.

    Published in Philippine studies.
    Article

    Narrating the dictator(ship) social memory, Marcos and Ilokano literature after the 1986 revolution.
  4. 1064

    Effects of microwave and mobile-telephone exposure on memory processes. by Lin, James C.

    Article

    Effects of microwave and mobile-telephone exposure on memory processes.
  5. 1065

    Algorithm 809: PREQN Fortran 77 subroutines for preconditioning the conjugate gradient method. by Morales, José Luis

    Article

    Algorithm 809: PREQN Fortran 77 subroutines for preconditioning the conjugate gradient method.
  6. 1066

    A specification-based approach to reasoning about pointers. by Kulczycki, Gregory

    Article

    A specification-based approach to reasoning about pointers.
  7. 1067

    An efficient and backwards-compatible transformation to ensure memory safety of C programs. by Xu, Wei

    Article

    An efficient and backwards-compatible transformation to ensure memory safety of C programs.
  8. 1068

    A combined input and output queued packet switched system based on PRIZMA switch on a chip technology. by Minkenberg, C.

    Article

    A combined input and output queued packet switched system based on PRIZMA switch on a chip technology.
  9. 1069

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache by Alidio, Lianne

    Thesis

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache
  10. 1070

    A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications. by Enomoto, T.

    Article

    A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications.

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