Toon 161 - 170 resultaten van 171 Voor zoekopdracht '"Very large scale integration."', zoektijd: 0,02s Verfijn jouw resultaten
  1. 161

    VLSI implementation of new arithmetic residue to binary decoders. door Hiasat, A.A

    Artikel

    VLSI implementation of new arithmetic residue to binary decoders.
  2. 162

    The effect of LUT and cluster size on deep-submicron FPGA performance and density. door Ahmed, E.

    Artikel

    The effect of LUT and cluster size on deep-submicron FPGA performance and density.
  3. 163

    Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. door Maheshwari, A.

    Artikel

    Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits.
  4. 164

    A generic applied evolutionary hybrid technique. door Beligiannis, G.

    Artikel

    A generic applied evolutionary hybrid technique.
  5. 165

    A VLSI architecture for visible watermarking in a secure still digital camera (S2DC) design (Corrected). door Mohanty, S.P

    Artikel

    A VLSI architecture for visible watermarking in a secure still digital camera (S2DC) design (Corrected).
  6. 166

    Optimization of throughput performance for low-power VLSI interconnects. door Deodhar, V.V

    Artikel

    Optimization of throughput performance for low-power VLSI interconnects.
  7. 167

    Design of wireless on-wafer submicron characterization system. door Moore, B.

    Artikel

    Design of wireless on-wafer submicron characterization system.
  8. 168

    A recursive MISD architecture for pattern matching. door Halaas, A.

    Artikel

    A recursive MISD architecture for pattern matching.
  9. 169

    Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. door Pomeranz, I.

    Artikel

    Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
  10. 170

    Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. door Chatterjee, B.

    Artikel

    Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.

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