Результаты поиска

1

Network on a chip modeling wireless networks with asynchronous VLSI. по Manohar, R.

Опубликовано в: IEEE Communications magazine

Статья

2

Efficient reconfigurable techniques for VLSI arrays with 6-port switches. по Wu Jigang

Опубликовано в: IEEE Transactions on VLSI systems

Статья

3

A faster linear systolic algorithm for recovering a longest common subsequence. по Lecroq, Thierry

Опубликовано в: Information processing letters.

Статья

4

Design of wireless on-wafer submicron characterization system. по Moore, B.

Опубликовано в: IEEE Transactions on VLSI systems

Статья

5

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. по Dobkin, R.

Опубликовано в: IEEE Transactions on VLSI systems

Статья

6

Design rewiring using ATPG. по Veneris, A.

Опубликовано в: IEEE Transactions on computer-aided design of integrated circuits and systems

Статья

7

A VLSI architecture for watermarking in a secure still digital camera (S2DC) design. по Mohanty, S.P

Опубликовано в: IEEE Transactions on VLSI systems

Статья

8

High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. по Meng-Da Yang

Опубликовано в: IEEE Transactions on VLSI systems

Статья

9

Application-specific array processors for the longest common subsequence problem of three sequences. по Luce, Guillaume

Опубликовано в: Parallel algorithms and applications.

Статья

10

A recursive MISD architecture for pattern matching. по Halaas, A.

Опубликовано в: IEEE Transactions on VLSI systems

Статья

Результаты поиска - "VLSI."

Network on a chip modeling wireless networks with asynchronous VLSI. по Manohar, R.

Efficient reconfigurable techniques for VLSI arrays with 6-port switches. по Wu Jigang

A faster linear systolic algorithm for recovering a longest common subsequence. по Lecroq, Thierry

Design of wireless on-wafer submicron characterization system. по Moore, B.

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. по Dobkin, R.

Design rewiring using ATPG. по Veneris, A.

A VLSI architecture for watermarking in a secure still digital camera (S2DC) design. по Mohanty, S.P

High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. по Meng-Da Yang

Application-specific array processors for the longest common subsequence problem of three sequences. по Luce, Guillaume

A recursive MISD architecture for pattern matching. по Halaas, A.

Инструменты поиска:

Отмена результатов

CAMPUS

DATABASE

UNIT LIBRARY

RESOURCE TYPE

AUTHOR

LANGUAGE