Mostrar 1 - 4 resultats de 4 per cerca '"VLSI implementations."', hora de la petició: 0.02sec Refinar resultats
  1. 1

    Iterative decoder architectures. per Yeo, Engling

    Article

    Iterative decoder architectures.
  2. 2

    VLSI implementation of a signal recognition and code acquisition algorithm for CDMA packet receivers. per Fanucci, L.

    Article

    VLSI implementation of a signal recognition and code acquisition algorithm for CDMA packet receivers.
  3. 3

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. per Dobkin, R.

    Article

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.
  4. 4

    A digit-serial multiplier for finite field GF(2m). per Chang Hoon Kim

    Article

    A digit-serial multiplier for finite field GF(2m).

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