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Switch-factor based loop RLC modeling for efficient timing analysis.
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Yu Cao
Udgivet i
IEEE Transactions on VLSI systems
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DATABASE
Union Catalog (Buklod)
11 results
11
AUTHOR
Yu Cao
2 results
2
Blunno, I.
1 results
1
Dianxiang Xu
1 results
1
Kim, C.J
1 results
1
Krstic, A.
1 results
1
Seong-Ook Jung
1 results
1
Taskin, B.
1 results
1
Tugsinavisut, S.
1 results
1
Valentian, A.
1 results
1
Xuejue Huang
1 results
1
se alt...
RESOURCE TYPE
Article
11 results
11
LANGUAGE
English
11 results
11
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