Отображение 1 - 10 результаты of 10 для поиска '"Test patterns generation."', время запроса: 0.02сек. Отмена результатов
  1. 1

    Testing big chips becomes an internal affair. по Runyon, S.

    Опубликовано в: IEEE spectrum
    Статья

    Testing big chips becomes an internal affair.
  2. 2

    Test pattern generation and clock disabling for simultaneous test time and power reduction. по Jih-Jeen Chen

    Статья

    Test pattern generation and clock disabling for simultaneous test time and power reduction.
  3. 3

    SPIRIT a highly robust combinational test generation algorithm. по Gizdarski, E.

    Статья

    SPIRIT a highly robust combinational test generation algorithm.
  4. 4

    Diagnosis of single stuck-at faults and multiple timing faults in scan chains. по Chien-Mo Li, J.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Diagnosis of single stuck-at faults and multiple timing faults in scan chains.
  5. 5

    Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. по Efthymiou, A.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.
  6. 6

    Function-based compact test pattern generation for path delay faults. по Michael, M.K

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Function-based compact test pattern generation for path delay faults.
  7. 7

    Design of hierarchical cellular automata for on-chip test pattern generator. по Sikdar, B.K

    Статья

    Design of hierarchical cellular automata for on-chip test pattern generator.
  8. 8

    On the nonenumerative path delay fault simulation problem. по Kagaris, D.

    Статья

    On the nonenumerative path delay fault simulation problem.
  9. 9

    Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams. по Ghosh, I.

    Статья

    Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams.
  10. 10

    Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time. по Voyiatzis, I.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time.

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