يعرض 1 - 10 نتائج من 10 نتيجة بحث عن '"Test pattern generation."', وقت الاستعلام: 0.02s تنقيح النتائج
  1. 1

    Testing big chips becomes an internal affair. حسب Runyon, S.

    الحاوية / القاعدة IEEE spectrum
    مقال

    Testing big chips becomes an internal affair.
  2. 2

    Test pattern generation and clock disabling for simultaneous test time and power reduction. حسب Jih-Jeen Chen

    مقال

    Test pattern generation and clock disabling for simultaneous test time and power reduction.
  3. 3

    SPIRIT a highly robust combinational test generation algorithm. حسب Gizdarski, E.

    مقال

    SPIRIT a highly robust combinational test generation algorithm.
  4. 4

    Diagnosis of single stuck-at faults and multiple timing faults in scan chains. حسب Chien-Mo Li, J.

    الحاوية / القاعدة IEEE Transactions on VLSI systems
    مقال

    Diagnosis of single stuck-at faults and multiple timing faults in scan chains.
  5. 5

    Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. حسب Efthymiou, A.

    الحاوية / القاعدة IEEE Transactions on VLSI systems
    مقال

    Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.
  6. 6

    Function-based compact test pattern generation for path delay faults. حسب Michael, M.K

    الحاوية / القاعدة IEEE Transactions on VLSI systems
    مقال

    Function-based compact test pattern generation for path delay faults.
  7. 7

    Design of hierarchical cellular automata for on-chip test pattern generator. حسب Sikdar, B.K

    مقال

    Design of hierarchical cellular automata for on-chip test pattern generator.
  8. 8

    On the nonenumerative path delay fault simulation problem. حسب Kagaris, D.

    مقال

    On the nonenumerative path delay fault simulation problem.
  9. 9

    Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams. حسب Ghosh, I.

    مقال

    Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams.
  10. 10

    Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time. حسب Voyiatzis, I.

    الحاوية / القاعدة IEEE Transactions on VLSI systems
    مقال

    Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time.

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