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Rezultati - "Test application time."
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A unified approach to reduce SOC test data volume, scan power and testing time.
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Chandra, A.
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IEEE Transactions on computer-aided design of integrated circuits and systems
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Test pattern generation and clock disabling for simultaneous test time and power reduction.
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Jih-Jeen Chen
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IEEE Transactions on computer-aided design of integrated circuits and systems
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Nine-coded compression technique for testing embedded cores in SoCs.
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Tehranipoor, M.
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IEEE Transactions on VLSI systems
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Testing ASICs with multiple identical cores.
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Yuejian Wu
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Testing of core-based systems-on-a-chip.
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Ravi, S.
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DATABASE
Union Catalog (Buklod)
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AUTHOR
Chandra, A.
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Jih-Jeen Chen
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Ravi, S.
1 results
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Tehranipoor, M.
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Yuejian Wu
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RESOURCE TYPE
Article
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LANGUAGE
English
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