検索結果 31 - 38 結果 / 38 検索語 '"Systems on a chip."', 処理時間: 0.02秒 結果の絞り込み
  1. 31

    A high-speed and low-voltage associative co-processor with exact Hamming 著者: Oike, Y.

    論文

    A high-speed and low-voltage associative co-processor with exact Hamming
  2. 32

    An architecture and compiler for scalable on-chip communication. 著者: Jian Liang

    論文

    An architecture and compiler for scalable on-chip communication.
  3. 33

    Automatic interconnection rectification for SoC design verification based on the port order fault model. 著者: Chun-Yao Wang

    論文

    Automatic interconnection rectification for SoC design verification based on the port order fault model.
  4. 34

    System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. 著者: Iyengar, V.

    論文

    System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.
  5. 35

    System-on-a-chip test-data compression and decompression architectures based on Golomb codes. 著者: Chandra, A.

    論文

    System-on-a-chip test-data compression and decompression architectures based on Golomb codes.
  6. 36

    Testing of core-based systems-on-a-chip. 著者: Ravi, S.

    論文

    Testing of core-based systems-on-a-chip.
  7. 37

    GALDS a complete framework for designing multiclock ASICs and SoCs. 著者: Chattopadhyay, A.

    論文

    GALDS a complete framework for designing multiclock ASICs and SoCs.
  8. 38

    Global interconnect design in a three-dimensional system-on-a-chip. 著者: Joyner, J.W

    論文

    Global interconnect design in a three-dimensional system-on-a-chip.

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