System-on-chip next generation electronics

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A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN. 著者: Vassiliou, I.

Test and measurement [Technology 2000 analysis and forecast]. 著者: Bretz, E.A

Calibrating simulation tools for nanometer designs. 著者: Shahram, M.

Design tools for analog and digital ICs. 著者: Geppert, L.

Testing big chips becomes an internal affair. 著者: Runyon, S.

A unified approach to reduce SOC test data volume, scan power and testing time. 著者: Chandra, A.

Test pattern generation and clock disabling for simultaneous test time and power reduction. 著者: Jih-Jeen Chen

Memory binding for performance optimization of control-flow intensive behavioral descriptions. 著者: Khouri, K.S

Virtual benchmarking and model continuity in prototyping embedded multiprocessor signal processing systems. 著者: Janka, R.S