Erakusten 1 - 10 emaitzak -- 38 bilaketa honetara '"System-on-chip."', Bilaketaren denbora: 0,02s Findu emaitzak
  1. 1

    A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip. nork Serra-Graells, F.

    Artikulua

    A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip.
  2. 2

    A direct-sequence spread-spectrum communication system for integrated sensor microsystems. nork Aydin, N.

    Artikulua

    A direct-sequence spread-spectrum communication system for integrated sensor microsystems.
  3. 3

    Layout conscious approach and bus architecture synthesis for hardware nork Thepayasuwan, N.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Layout conscious approach and bus architecture synthesis for hardware
  4. 4

    A robust self-calibrating transmission scheme for on-chip networks. nork Worm, F.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    A robust self-calibrating transmission scheme for on-chip networks.
  5. 5

    Synchronization overhead in SOC compressed test. nork Gonciari, P.T

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Synchronization overhead in SOC compressed test.
  6. 6

    Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. nork Yu Cao

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design.
  7. 7

    SOC test planning using virtual test access architectures. nork Sehgal, A.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    SOC test planning using virtual test access architectures.
  8. 8

    Baud-rate channel equalization in nanometer technologies. nork Chou, E.Y

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Baud-rate channel equalization in nanometer technologies.
  9. 9

    Robust interfaces for mixed-timing systems. nork Chelcea, T.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Robust interfaces for mixed-timing systems.
  10. 10

    Fixed-outline floorplanning enabling hierarchical design. nork Adya, S.N

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Fixed-outline floorplanning enabling hierarchical design.

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