Search Results - "Speed."

211

A second-order semidigital clock recovery circuit based on injection locking. by Hiok-Tiaq Ng

Published in IEEE Journal of solid state circuits

Article

A second-order semidigital clock recovery circuit based on injection locking.

212

An 8-Gb by Casper, B.

Published in IEEE Journal of solid state circuits

Article

213

Broadband ESD protection circuits in CMOS technology. by Galal, S.

Published in IEEE Journal of solid state circuits

Article

Broadband ESD protection circuits in CMOS technology.

214

A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS. by Uyttenhove, K.

Published in IEEE Journal of solid state circuits

Article

A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS.

215

Mobile multi-user ATM platforms architectures, design issues, and challenges. by Kumar, P.

Published in IEEE Network : the magazine of global information exchange

Article

Mobile multi-user ATM platforms architectures, design issues, and challenges.

216

High speed storage area networks using a fibre channel arbitrated loop interconnect. by Heath, J.R

Published in IEEE Network : the magazine of global information exchange

Article

High speed storage area networks using a fibre channel arbitrated loop interconnect.

217

An IP transport and routing architecture for next-generation satellite networks. by Yegenoglu, F.

Published in IEEE Network : the magazine of global information exchange

Article

An IP transport and routing architecture for next-generation satellite networks.

218

An evaluation of the key design criteria to achieve high update rates in packet classifiers. by Macian, C.

Published in IEEE Network : the magazine of global information exchange

Article

An evaluation of the key design criteria to achieve high update rates in packet classifiers.

219

On the message and time complexity of protocols for reliable broadcasts by Hong-Yi Tzeng

Published in IEEE Journal on selected areas in communications

Article

On the message and time complexity of protocols for reliable broadcasts

220

The effect of bandwidth allocation policies on delay in unidirectional bus networks. by Manjunath, D.

Published in IEEE Journal on selected areas in communications

Article

A second-order semidigital clock recovery circuit based on injection locking. by Hiok-Tiaq Ng

An 8-Gb by Casper, B.

Broadband ESD protection circuits in CMOS technology. by Galal, S.

A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS. by Uyttenhove, K.

Mobile multi-user ATM platforms architectures, design issues, and challenges. by Kumar, P.

High speed storage area networks using a fibre channel arbitrated loop interconnect. by Heath, J.R

An IP transport and routing architecture for next-generation satellite networks. by Yegenoglu, F.

An evaluation of the key design criteria to achieve high update rates in packet classifiers. by Macian, C.

On the message and time complexity of protocols for reliable broadcasts by Hong-Yi Tzeng

The effect of bandwidth allocation policies on delay in unidirectional bus networks. by Manjunath, D.

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