Search Results - "SoC."

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  1. 1

    NComputing 3-in-1 device. IN Tech 101. by Inocentes, Carl Rogel

    Published in Manila Bulletin
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  2. 2

    Automatic interconnection rectification for SoC design verification based on the port order fault model. by Chun-Yao Wang

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  3. 3

    Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. by Kanno, Y.

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  4. 4

    Design-for-testability for embedded delay-locked loops. by Egan, T.

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  5. 5

    Crossroads for mixed-signal chips. by Levin, P.L

    Published in IEEE spectrum
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  6. 6

    Crossroads for mixed-signal chips. by Levin, P.L

    Published in IEEE spectrum
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  7. 7

    Crossroads for mixed-signal chips. by Levin, P.L

    Published in IEEE spectrum
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  8. 8

    A multiparameter implantable microstimulator SOC. by Chua-Chin Wang

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  9. 9

    Fixed-outline floorplanning enabling hierarchical design. by Adya, S.N

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  10. 10

    Test pattern generation and clock disabling for simultaneous test time and power reduction. by Jih-Jeen Chen

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