Search Results - "SiON."

101

A jitter characterization system using a component-invariant Vernier delay line. by Chan, A.H

Published in IEEE Transactions on VLSI systems

Article

A jitter characterization system using a component-invariant Vernier delay line.

102

A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor. by Walkey, D.J

Published in IEEE Transactions on computer-aided design of integrated circuits and systems

Article

A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor.

103

Scaling of strained-Si n-MOSFETs into the ballistic regime and associated anisotropic effects. by Bufler, F.M

Published in IEEE Transactions on electron devices

Article

Scaling of strained-Si n-MOSFETs into the ballistic regime and associated anisotropic effects.

104

Monte Carlo simulation and measurement of nanoscale n-MOSFETs. by Bufler, F.M

Published in IEEE Transactions on electron devices

Article

Monte Carlo simulation and measurement of nanoscale n-MOSFETs.

105

Effect of band alignment and density of states on the collector current in p-Si/n-Si1-yCy by Singh, D.V

Published in IEEE Transactions on electron devices

Article

Effect of band alignment and density of states on the collector current in p-Si/n-Si1-yCy

106

Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack its tradeoff with gate capacitance. by Yang-Yu Fan

Published in IEEE Transactions on electron devices

Article

Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack its tradeoff with gate capacitance.

107

Development of high-current 4H-SiC ACCUFET. by Singh, R.

Published in IEEE Transactions on electron devices

Article

Development of high-current 4H-SiC ACCUFET.

108

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications. by Afzalian, A.

Published in IEEE Transactions on electron devices

Article

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications.

109

Amorphous silicon active pixel sensor readout circuit for digital imaging. by Karim, K.S

Published in IEEE Transactions on electron devices

Article

Amorphous silicon active pixel sensor readout circuit for digital imaging.

110

Two-dimensional monolithic lead chalcogenide infrared sensor arrays on silicon read-out chips and noise mechanisms. by Zogg, H.

Published in IEEE Transactions on electron devices

Article

A jitter characterization system using a component-invariant Vernier delay line. by Chan, A.H

A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor. by Walkey, D.J

Scaling of strained-Si n-MOSFETs into the ballistic regime and associated anisotropic effects. by Bufler, F.M

Monte Carlo simulation and measurement of nanoscale n-MOSFETs. by Bufler, F.M

Effect of band alignment and density of states on the collector current in p-Si/n-Si1-yCy by Singh, D.V

Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack its tradeoff with gate capacitance. by Yang-Yu Fan

Development of high-current 4H-SiC ACCUFET. by Singh, R.

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications. by Afzalian, A.

Amorphous silicon active pixel sensor readout circuit for digital imaging. by Karim, K.S

Two-dimensional monolithic lead chalcogenide infrared sensor arrays on silicon read-out chips and noise mechanisms. by Zogg, H.

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