Showing 21 - 27 results of 27 for search '"SRAM."', query time: 0.01s Refine Results
  1. 21

    Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs. by Hua Wang

    Article

    Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.
  2. 22

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. by Inokawa, H.

    Article

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors.
  3. 23

    A Case for Asymmetric-Cell Cache Memories. by Moshovos, A.

    Article

    A Case for Asymmetric-Cell Cache Memories.
  4. 24

    A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. by Chua-Chin Wang

    Article

    A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.
  5. 25

    Circuit and microarchitectural techniques for reducing cache leakage power. by Nam Sung Kim

    Article

    Circuit and microarchitectural techniques for reducing cache leakage power.
  6. 26

    PD by Joshi, R.V

    Article

    PD
  7. 27

    Circuits and architectures for field programmable gate array with configurable supply voltage. by Lin, Y.

    Article

    Circuits and architectures for field programmable gate array with configurable supply voltage.

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