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Threshold voltage-related soft error degradation in a TFT SRAM cell.
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Ikeda, S.
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IEEE Transactions on electron devices
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A process-tolerant cache architecture for improved yield in nanoscale technologies.
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Agarwal, A.
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Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.
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Yen-Jen Chang
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A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.
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Khellah, M.
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IEEE Journal of solid state circuits
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A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations.
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Kim, C.H
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Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
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Qikai Chen
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A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.
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Chua-Chin Wang
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Circuits and architectures for field programmable gate array with configurable supply voltage.
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Lin, Y.
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DATABASE
Union Catalog (Buklod)
8 results
8
AUTHOR
Agarwal, A.
1 results
1
Chua-Chin Wang
1 results
1
Ikeda, S.
1 results
1
Khellah, M.
1 results
1
Kim, C.H
1 results
1
Lin, Y.
1 results
1
Qikai Chen
1 results
1
Yen-Jen Chang
1 results
1
see all…
RESOURCE TYPE
Article
8 results
8
LANGUAGE
English
8 results
8
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