Search Results - "Power reduction."

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  1. 1

    Distributed sleep transistor network for power reduction. by Changbo Long

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  2. 2

    Quantitative analysis and optimization techniques for on-chip cache leakage power. by Nam Sung Kim

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  3. 3

    Low-power scan design using first-level supply gating. by Bhunia, S.

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  4. 4

    A temperature-insensitive self-recharging circuitry used in DRAMs. by Chua-Chin Wang

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  5. 5

    Bus encoding for total power reduction using a leakage-aware buffer configuration. by Rao, R.R

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  6. 6

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design by Zarsuela, Jestoni V.

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  7. 7

    Characterization and modeling of run-time techniques for leakage power reduction. by Yuh-Fang Tsai

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  8. 8

    DCG deterministic clock-gating for low-power microprocessor design. by Hai Li

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  9. 9

    DLS dynamic backlight luminance scaling of liquid crystal display. by Naehyuck Chang

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  10. 10

    Soft errors issues in low-power caches. by Degalahal, V.

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