Canlyniadau Chwilio - "Power reduction."

Mireinio'r Canlyniadau
  1. 1

    Distributed sleep transistor network for power reduction. gan Changbo Long

    Erthygl


    Delwedd Flaen
  2. 2

    Quantitative analysis and optimization techniques for on-chip cache leakage power. gan Nam Sung Kim

    Erthygl


    Delwedd Flaen
  3. 3

    Low-power scan design using first-level supply gating. gan Bhunia, S.

    Erthygl


    Delwedd Flaen
  4. 4

    A temperature-insensitive self-recharging circuitry used in DRAMs. gan Chua-Chin Wang

    Erthygl


    Delwedd Flaen
  5. 5

    Bus encoding for total power reduction using a leakage-aware buffer configuration. gan Rao, R.R

    Erthygl


    Delwedd Flaen
  6. 6

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design gan Zarsuela, Jestoni V.

    Traethawd Ymchwil


    Delwedd Flaen
  7. 7

    Characterization and modeling of run-time techniques for leakage power reduction. gan Yuh-Fang Tsai

    Erthygl


    Delwedd Flaen
  8. 8

    DCG deterministic clock-gating for low-power microprocessor design. gan Hai Li

    Erthygl


    Delwedd Flaen
  9. 9

    DLS dynamic backlight luminance scaling of liquid crystal display. gan Naehyuck Chang

    Erthygl


    Delwedd Flaen
  10. 10

    Soft errors issues in low-power caches. gan Degalahal, V.

    Erthygl


    Delwedd Flaen

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