Mostrando 21 - 30 resultados de 38 para a busca '"Phase locked loops."', tempo de busca: 0.02s Refinar Resultados
  1. 21

    A slew-rate controlled output driver using PLL as compensation circuit. por Soon-Kyun Shin

    Artigo

    A slew-rate controlled output driver using PLL as compensation circuit.
  2. 22

    A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000 por Van Veldhoven, R.H.M

    Artigo

    A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000
  3. 23

    A fully integrated zero-IF transceiver for GSM-GPRS quad-band application. por Duvivier, E.

    Artigo

    A fully integrated zero-IF transceiver for GSM-GPRS quad-band application.
  4. 24

    Techniques for phase noise suppression in recirculating DLLs. por Sheng Ye

    Artigo

    Techniques for phase noise suppression in recirculating DLLs.
  5. 25

    A 39-to-45-Gbit por Nosaka, H.

    Artigo

    A 39-to-45-Gbit
  6. 26

    A 20-GHz phase-locked loop for 40-gb por Jaeha Kim

    Artigo

    A 20-GHz phase-locked loop for 40-gb
  7. 27

    Anti-hangup binary quantized DPLL technique for timing recovery in QAM symbol-rate sampled receivers. por Panayiotopoulos, I.

    Artigo

    Anti-hangup binary quantized DPLL technique for timing recovery in QAM symbol-rate sampled receivers.
  8. 28

    Design of a low power wide-band high resolution programmable frequency divider. por Yu, X.P

    Artigo

    Design of a low power wide-band high resolution programmable frequency divider.
  9. 29

    A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS. por Da Dalt, N.

    Artigo

    A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS.
  10. 30

    STS-768 multiplexer with full-rate output data retimer in InP HBT. por Hendarman, A.

    Artigo

    STS-768 multiplexer with full-rate output data retimer in InP HBT.

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