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2631
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2632
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2633
Dynamic control of a fixed pattern rectifier.
Argitaratua izan da IEEE Transactions on power electronicsArtikulua -
2634
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2635
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2636
A review of 0.18-μm full adder performances for tree structured arithmetic circuits.
Argitaratua izan da IEEE Transactions on VLSI systemsArtikulua -
2637
An efficient merging scheme for prescribed skew clock routing.
Argitaratua izan da IEEE Transactions on VLSI systemsArtikulua -
2638
Analysis of load frequency control performance assessment criteria.
Argitaratua izan da IEEE Transactions on power systemsArtikulua -
2639
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.
Argitaratua izan da IEEE Transactions on VLSI systemsArtikulua -
2640
VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
Argitaratua izan da IEEE Transactions on VLSI systemsArtikulua