Showing 381 - 390 results of 440 for search '"Parallelism."', query time: 0.02s Refine Results
  1. 381

    Parallel Programmable Ethernet Controllers Performance and Security. by Schuff, D.L

    Article

    Parallel Programmable Ethernet Controllers Performance and Security.
  2. 382

    Parallel structures for joint channel estimation and data detection over fading channels. by Omidi, M.J

    Article

    Parallel structures for joint channel estimation and data detection over fading channels.
  3. 383

    VLSI implementation of a signal recognition and code acquisition algorithm for CDMA packet receivers. by Fanucci, L.

    Article

    VLSI implementation of a signal recognition and code acquisition algorithm for CDMA packet receivers.
  4. 384

    A DSP-based DS-CDMA multiuser receiver employing partial parallel interference cancellation. by Correal, N.S

    Article

    A DSP-based DS-CDMA multiuser receiver employing partial parallel interference cancellation.
  5. 385

    Little robotic autos that can.

    Published in IEEE spectrum
    Article

    Little robotic autos that can.
  6. 386

    Adaptive multistage parallel interference cancellation for CDMA. by Guoqiang Xue

    Article

    Adaptive multistage parallel interference cancellation for CDMA.
  7. 387

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. by Dobkin, R.

    Article

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.
  8. 388

    Design of multigigabit multiplexer-loop-based decision feedback equalizers. by Parhi, K.K

    Article

    Design of multigigabit multiplexer-loop-based decision feedback equalizers.
  9. 389

    Design of a 3-D fully depleted SOI computational RAM. by Koob, J.C

    Article

    Design of a 3-D fully depleted SOI computational RAM.
  10. 390

    Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. by Shin, K.

    Article

    Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.

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