Showing 571 - 580 results of 711 for search '"Multiplication"', query time: 0.02s Refine Results
  1. 571

    Wrapper design for multifrequency IP cores. by Qiang Xu

    Article

    Wrapper design for multifrequency IP cores.
  2. 572

    Diagnosis of single stuck-at faults and multiple timing faults in scan chains. by Chien-Mo Li, J.

    Article

    Diagnosis of single stuck-at faults and multiple timing faults in scan chains.
  3. 573

    Nine-coded compression technique for testing embedded cores in SoCs. by Tehranipoor, M.

    Article

    Nine-coded compression technique for testing embedded cores in SoCs.
  4. 574

    Time-varying contingency screening for dynamic security assessment using intelligent-systems techniques. by Kamwa, I.

    Article

    Time-varying contingency screening for dynamic security assessment using intelligent-systems techniques.
  5. 575

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. by Dobkin, R.

    Article

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.
  6. 576

    Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication. by Tugsinavisut, S.

    Article

    Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication.
  7. 577

    A digit-serial multiplier for finite field GF(2m). by Chang Hoon Kim

    Article

    A digit-serial multiplier for finite field GF(2m).
  8. 578

    Efficient shield insertion for inductive noise reduction in nanometer technologies. by Elgamel, M.A

    Article

    Efficient shield insertion for inductive noise reduction in nanometer technologies.
  9. 579

    A multicarrier QAM modulator for WCDMA base-station with on-chip D by Kosunen, M.

    Article

    A multicarrier QAM modulator for WCDMA base-station with on-chip D
  10. 580

    A "Flying-Adder" frequency synthesis architecture of reducing VCO stages. by Liming Xiu

    Article

    A "Flying-Adder" frequency synthesis architecture of reducing VCO stages.

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