Dangos 10,821 - 10,830 canlyniadau o 11,409 ar gyfer chwilio '"Modelling."', amser ymholiad: 0.04e Mireinio'r Canlyniadau
  1. 10821

    Extraction and use of neural network models in automated synthesis of operational amplifiers. gan Wolfe, G.

    Erthygl

    Extraction and use of neural network models in automated synthesis of operational amplifiers.
  2. 10822

    A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor. gan Walkey, D.J

    Erthygl

    A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor.
  3. 10823

    Fast on-chip inductance simulation using a precorrected-FFT method. gan Hu, H.

    Erthygl

    Fast on-chip inductance simulation using a precorrected-FFT method.
  4. 10824

    Chip-level charged-device modeling and simulation in CMOS integrated circuits. gan Jaesik Lee

    Erthygl

    Chip-level charged-device modeling and simulation in CMOS integrated circuits.
  5. 10825

    Maze routing with buffer insertion under transition time constraints. gan Li-Da Huang

    Erthygl

    Maze routing with buffer insertion under transition time constraints.
  6. 10826

    Automatic interconnection rectification for SoC design verification based on the port order fault model. gan Chun-Yao Wang

    Erthygl

    Automatic interconnection rectification for SoC design verification based on the port order fault model.
  7. 10827

    Renormalization group meshes and the discretization of TCAD equations. gan Schoenmaker, W.

    Erthygl

    Renormalization group meshes and the discretization of TCAD equations.
  8. 10828

    Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications. gan Gao, X.F

    Erthygl

    Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications.
  9. 10829

    Test vector generation for charge sharing failures in dynamic logic. gan Heragu, K.

    Erthygl

    Test vector generation for charge sharing failures in dynamic logic.
  10. 10830

    Formulating SoC test scheduling as a network transportation problem. gan Koranne, S.

    Erthygl

    Formulating SoC test scheduling as a network transportation problem.

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