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Physical random number generator based on MOS structure after soft breakdown.
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Yasuda, S.
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Substrate coupling in digital circuits in mixed-signal smart-power systems.
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A jitter characterization system using a component-invariant Vernier delay line.
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Reducing voltage sags through fault current limitation.
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A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.
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A framework for energy and transient power reduction during behavioral synthesis.
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