Showing 1 - 10 results of 10 for search '"Memory accesses."', זמן שאילתה: 0.02s Refine Results
  1. 1

    Gigabit Ethernet switches using a shared buffer architecture. מאת Lau, M.V

    הוצא לאור ב IEEE Communications magazine
    Article

    Gigabit Ethernet switches using a shared buffer architecture.
  2. 2

    Dissemination of routing information in broadcast networks OSPF versus IS-IS. מאת Sharon, O.

    Article

    Dissemination of routing information in broadcast networks OSPF versus IS-IS.
  3. 3

    A single mediaprocessor-based programmable ultrasound system. מאת Sikdar, S.

    Article

    A single mediaprocessor-based programmable ultrasound system.
  4. 4

    The CSI multimedia architecture. מאת Cheresiz, D.

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    The CSI multimedia architecture.
  5. 5

    Memory-access-aware data structure transformations for embedded software with dynamic data accesses. מאת Daylight, E.G

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Memory-access-aware data structure transformations for embedded software with dynamic data accesses.
  6. 6

    Compiler-directed scratch pad memory optimization for embedded multiprocessors. מאת Kandemir, M.

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Compiler-directed scratch pad memory optimization for embedded multiprocessors.
  7. 7

    Multistage Switching Architectures for Software Routers. מאת Bianco, A.

    Article

    Multistage Switching Architectures for Software Routers.
  8. 8

    Quantitative analysis and optimization techniques for on-chip cache leakage power. מאת Nam Sung Kim

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Quantitative analysis and optimization techniques for on-chip cache leakage power.
  9. 9

    Fast maximum intensity projections of large medical data sets by exploiting hierarchical memory architectures. מאת Kiefer, G.

    Article

    Fast maximum intensity projections of large medical data sets by exploiting hierarchical memory architectures.
  10. 10

    FAIR a hardware architecture for real-time 3-D image registration. מאת Castro-Pareja, C.R

    Article

    FAIR a hardware architecture for real-time 3-D image registration.

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